Method of forming an electronic device using a separation technique

ABSTRACT

A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.

RELATED APPLICATION

This is a continuation of and claims priority under 35 U.S.C. §120 toU.S. patent application Ser. No. 12/467,035 entitled “Method of Formingan Electronic Device Using a Separation Technique” by Mathew et al. onMay 15, 2009, and is related to and claims priority under 35 U.S.C.§119(e) to U.S. Patent Application No. 61/054,139 entitled “Method ofForming Contacts on a Semiconductor Layer and Related Devices” by Mathewet al. on May 17, 2008, both of which are assigned to the currentassignee hereof and incorporated herein by reference in their entirety.

FIELD OF THE DISCLOSURE

The present invention relates generally to semiconductors, and inparticular to methods for making semiconductor devices on a layer thathas been separated from a substrate.

RELATED ART

The use of semiconductor layers that have been transferred ontosubstrates or substrates that have been thickened using various growthprocesses have been used in technologies such as silicon-on-insulator(SOI) technology. The transfer of layers therein involves processincorporation of a cleaving plane, sticking to a foreign substrate andseparation of the surface layer. The incorporation of a cleaving planeis performed using a process of ion implantation or formation of porouslayers. The bonding to a foreign substrate involves Van der Waals forceson extremely smooth surfaces; eutectic bonding using suitable materials;or thermo-compression bonding using suitable materials, elevatedtemperature, and elevated pressure. The separation involves annealing ofthe bubbles and cracks formed during ion implantation. In the formationof devices, the cycle time and cost of processes such as ionimplantation and the formation of smooth surfaces is expensive.

In the formation of an electronic device, junctions can be used forapplications, such as photovoltaic cells and light emitting diodes.Typically, the junctions are contacted on opposite sides of thesubstrate. In different applications, a plurality of contacts may liealong one side of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example and are not limited in theaccompanying figures.

FIG. 1 includes an illustration of a cross-sectional view of a portionof a workpiece after forming a separation-enhancing species within asubstrate.

FIG. 2 includes an illustration of a cross-sectional view of theworkpiece of FIG. 1 after forming a dielectric layer over and dopedregions within the substrate.

FIG. 2 includes an illustration of a cross-sectional view of theworkpiece of FIG. 1 after formation of a seed layer.

FIG. 3 includes an illustration of a cross-sectional view of theworkpiece of FIG. 2 after forming a metal-containing layer.

FIG. 4 includes an illustration of a cross-sectional view of theworkpiece of FIG. 3 after forming metal-containing regions from themetal-containing layer.

FIG. 5 includes an illustration of a cross-sectional view of theworkpiece of FIG. 4 after parts of the dielectric layer have beenreshaped.

FIG. 6 includes an illustration of a cross-sectional view of theworkpiece of FIG. 5 after forming metallic regions within openings ofthe dielectric layer.

FIG. 7 includes an illustration of a cross-sectional view of theworkpiece of FIG. 6 after separating a semiconductor layer from thesubstrate.

FIG. 8 includes an illustration of a cross-sectional view of theworkpiece of FIG. 7 after the forming a substantially completedsemiconductor device in accordance with an embodiment.

FIG. 9 includes an illustration of a cross-sectional view of anembodiment where semiconductor layers have been separated from oppositesides using any of procedures described with respect to FIG. 1 throughFIG. 7.

FIG. 10 includes an illustration of a cross-sectional view of theworkpiece of FIG. 8 after forming a reflector in accordance with anotherembodiment.

FIGS. 11 and 12 include illustrations of cross-sectional views ofportions of workpieces in accordance with alternative embodiments.

FIG. 13 includes an illustration of a cross-sectional view of a portionof a workpiece comprising a substrate, in ingot form, a doped region,and a conductive layer.

FIG. 14 includes an illustration of a cross-sectional view of theworkpiece of FIG. 13 after a combination of a semiconductor layer, thedoped region, the conductive layer has been separated from thesubstrate.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help to improveunderstanding of embodiments of the invention.

DETAILED DESCRIPTION

The following description in combination with the figures is provided toassist in understanding the teachings disclosed herein. The followingdiscussion will focus on specific implementations and embodiments of theteachings. This focus is provided to assist in describing the teachingsand should not be interpreted as a limitation on the scope orapplicability of the teachings. However, other teachings can certainlybe utilized in this application.

Before addressing details of embodiments described below, some terms aredefined or clarified. The term “metal” and any of its variants areintended to refer to a material that includes an element that is (1)within any of Groups 1 to 12, or (2) within Groups 13 to 15, an elementthat is along and below a line defined by atomic numbers 13 (Al), 50(Sn), and 83 (Bi), or any combination thereof. Metal does not includesilicon or germanium. Note, however, that a metal silicide is a metallicmaterial.

As used herein, the terms “comprises,” “comprising,” “includes,”“including,” “has,” “having” or any other variation thereof, areintended to cover a non-exclusive inclusion. For example, a method,article, or apparatus that comprises a list of features is notnecessarily limited only to those features but may include otherfeatures not expressly listed or inherent to such method, article, orapparatus. Further, unless expressly stated to the contrary, “or” refersto an inclusive-or and not to an exclusive-or. For example, a conditionA or B is satisfied by any one of the following: A is true (or present)and B is false (or not present), A is false (or not present) and B istrue (or present), and both A and B are true (or present).

Also, the use of “a” or “an” is employed to describe elements andcomponents described herein. This is done merely for convenience and togive a general sense of the scope of the invention. This descriptionshould be read to include one or at least one and the singular alsoincludes the plural, or vice versa, unless it is clear that it is meantotherwise. For example, when a single item is described herein, morethan one item may be used in place of a single item. Similarly, wheremore than one item is described herein, a single item may be substitutedfor that more than one item.

Group numbers corresponding to columns within the Periodic Table of theelements use the “New Notation” convention as seen in the CRC Handbookof Chemistry and Physics, 81^(st) Edition (2000-2001).

Unless otherwise defined, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this invention belongs. The materials, methods, andexamples are illustrative only and not intended to be limiting. To theextent not described herein, many details regarding specific materialsand processing acts are conventional and may be found in textbooks andother sources within the semiconductor and electronic arts.

A method of forming an electronic device can include forming a patternedlayer adjacent to a side of a substrate including a semiconductormaterial. The method can also include separating a semiconductor layerand the patterned layer from the substrate, wherein the semiconductorlayer is a portion of the substrate. In particular embodiments, theembodiments described herein can be used to forming contacts on one sideof a substrate while using separation technique to be performed. In aparticular embodiment, a separation-enhancing species to be introducedinto a substrate to allow more readily the separation of a surface layerof semiconductor material to be removed from the substrate. A mechanicaloperation may not need to be performed for the separation, or if amechanical operation is used, such mechanical operation would not needto be as aggressive or damaging as compared to a mechanical tearingoperation performed in the absence of the separation-enhancing species.Further, the doped regions and contacts can be formed along a sideopposite where light or other radiation would be received by anelectronic device. Thus, the efficiency is improved as contacts,interconnects, and the like are not formed along the radiation receivingsurface of the electronic device. Although the description belowprovides many details, including particular numerical values andconfigurations, after reading this specification, skilled artisans willappreciate that the embodiments described herein merely illustrate anddo not limit the scope of the present invention.

FIG. 1 illustrates a workpiece 100 comprising a substrate 102 having aprimary side 106 and an opposing side 110 along an opposite side of thesubstrate 102. The substrate may be a semiconductor substrate comprisinga Group 14 element (silicon, germanium, or carbon), any combination ofGroup 14 elements (silicon germanium, carbon-doped silicon, or thelike), or Group 13-Group 15 semiconductors (gallium arsenide, galliumnitride, indium phosphide, gallium indium arsenide, or the like). Thesubstrate 102 can include a substantially monocrystalline, amorphous, orpolycrystalline semiconductor substrate. In other embodiments, variouscombinations of materials may form the substrate. In a particularembodiment, the substrate can have a thickness of at least approximately50 microns or at least approximately 200 microns. Although there is notheoretical upper limit on the thickness, the substrate may be nogreater than approximately 5 meters or no greater than approximately 0.1meter. In subsequent figures, the portion of the substrate 102 near theopposing side 110 is not illustrated for simplicity. As will bedescribed in an alternative embodiment, ingot processing can be used toform substantially rectangular sheets.

A separation-enhancing species can be implanted to a depth 104 below theprimary side 106 of the substrate 102, as illustrated in FIG. 1. The ionimplantation can create defect sites, which during a subsequentseparation operation, help in separating a portion of the substrate 102including the primary side 106 from the remainder of the substrate 102to form a semiconductor layer. The depth 104 may be based at least onpart on the composition of substrate 102 and the particular electronicapplication, such as a photovoltaic cell, a light emitting device, aradiation detector, or the like. In a particular embodiment, theprojected range is substantially equal to the desired thickness of thesemiconductor layer that will be formed upon subsequent separation. Inan embodiment, the projected range is at least approximately 1 micron orat least approximately 20 microns, and in another embodiment, thesemiconductor layer can have a thickness no greater than approximately100 microns or no greater than approximately 50 microns.

The separation-enhancing species can include hydrogen, helium, boron,silicon, fluorine, chlorine, or the like. Although not limited to thoseelements, the relatively lighter species may allow the species to beimplanted relatively farther into the substrate 102 than if a relativelyheavier species (e.g., germanium or arsenic) were used. Thus, the damageto the substrate 102, and particularly the semiconductor layer that willbe subsequently separated from the substrate 102, may be less. After aparticular species is selected, an implant energy is determined toachieve a desired projected range corresponding to the depth 104. Theprojected range can lie closer to the primary side 106 of the substrate102 as compared to the opposing side 110. In a particular embodiment,the projected range is substantially equal to the desired thickness ofthe semiconductor layer that will be formed upon subsequent separation.The dose of the implant can be at least approximately 10¹⁵ ions/cm²,approximately 10¹⁶ ions/cm², or even higher.

In another embodiment, the separation-enhancing species can beintroduced later in the process flow or by using a different technique,such as an electrochemical process that is described later in thisspecification. In still another embodiment, a combination of thedifferent techniques may be used.

FIG. 1 includes an illustration of both the primary side 106 andopposing side 110 of the substrate 102. For simplicity, FIGS. 2 to 8 donot include the opposing 110 of the substrate 102, although the opposingside 110 still remains part of the substrate 102.

A dielectric layer 202 is formed over the substrate 102, and dopedregions 204 and 206 are formed within the substrate 102, as illustratedin FIG. 2. The dielectric layer 202 can be used to aid in the formationof subsequent contacts to the doped regions 204 and 206. The dielectriclayer 202 can include an oxide, a nitride, an oxynitride, or the likeand can be formed by growing or depositing a single film or a pluralityof films. In an embodiment, the dielectric layer 202 can have athickness of at least approximately 1 nm or at least approximately 1000nm, and in another embodiment, the dielectric layer 202 can have athickness no greater than approximately 1000 microns or no greater thanapproximately 100 microns.

The width of the openings or pattern of the openings in the patterneddielectric layer may be designed to enable the separation-enhancingspecies to be incorporated into the substrate 102 at a particular depthin the regions directly below the openings and at a different depth intothe substrate 102 at regions directly below remaining portions of thedielectric layer 202. The separation-enhancing species may form acontiguous region to enable a contiguous region of substrate 102 to beseparated.

The dielectric layer 202 is patterned to form a patterned dielectriclayer that defines openings to expose portions of the substrate 102where the doped regions 204 and 206 are formed. The openingscorresponding to the doped regions 204 and 206 may be formed atsubstantially the same time or at different times. In a particularembodiment, openings corresponding to the doped regions 204 are formed,and portions of the substrate 102 are doped to form the doped regions204, and then another opening corresponding to the doped region 206 isformed, and a portion of the substrate 102 is doped to form the dopedregion 206. In another embodiment, more or fewer doped regions may beformed. The doped regions 204 may be of the same conductivity type oropposite conductivity types. In an embodiment, the doped regions 204 maybe n-type doped, and the doped region 206 may be p-type doped. When thesubstrate 102 is p-type doped, the doped region 206 can be used as abody contact, and pn junctions are formed at the interfaces between thedoped regions 204 and substrate 102. Conductivity types can be reversedin another embodiment.

The doped regions 204 and 206 can be formed by gas-phase furnace doping,a spin-on dopant, depositing or growing a doped layer (a doped glass, adoped semiconductor layer (amorphous, polycrystalline, substantiallymonocrystalline), or by implantation. The doped regions 204 and 206 aretypically formed during separate doping sequences. An anneal or dopantdrive may be performed if needed or desired. In an embodiment, the peakconcentration of the doped regions 204 and 206 are at leastapproximately 10¹⁷, 10¹⁸, or 10¹⁹ atoms/cm³. In an embodiment, thejunction depths of the doped regions 204 and is at least approximately0.01 microns or at least approximately 0.1 microns, and in anotherembodiment, the junction depths of the doped regions 204 and 206 are nogreater than approximately 5 microns or no greater than approximately 1micron. If the dopant source for the doped regions 204 or 206 includes alayer formed over the substrate 102, the layer may or may not be removedafter the corresponding doped regions are formed. For example, a dopedsilicon layer may be formed over the substrate 102 and remain. In aparticular embodiment, the doped regions 204 or 206 may principally liewithin the doped silicon layer. As between the doped region 206 and thedoped regions 204, they can have the same dopant concentration ordifferent dopant concentrations, and the same junction depth ordifferent junction depths, and can be formed with the same dopingtechnique or different doping techniques.

A metal-containing layer 302 is formed over the dielectric layer 202 andthe doped regions 204 and 206, as illustrated in FIG. 3. Themetal-containing layer 302 can include an adhesion film, a barrier film,a seed film, another suitable film, or any combination thereof. Theadhesion film can include a refractory metal (titanium, tantalum,tungsten, or the like), and the barrier film can include a metal nitride(TiN, TaN, WN of the like) or a metal semiconductor nitride (TaSiN,WSiN, or the like). The seed film can include a transition metal ortransition metal alloy, and in a particular embodiment, the seed filmcan include titanium, nickel, palladium, tungsten, copper, silver, orgold. In other embodiments, other materials may be used within theadhesion film, barrier film, seed film, or any combination thereof. Themetal-containing layer 302 can be formed by physical vapor deposition(PVD, such as evaporation or sputtering), chemical vapor deposition(CVD), atomic layer deposition (ALD), electrochemistry, another suitablemethod, or any combination thereof. In an embodiment, themetal-containing layer 302 can have a thickness of at leastapproximately 1 nm or at least approximately 10 nm, and in anotherembodiment, the metal-containing layer 302 can have a thickness nogreater than approximately 10 microns or no greater than approximately0.1 microns

In a particular embodiment, the metal-containing layer 302 may be bondedto the doped regions 204 and 206 by reacting the metal-containing layer302 with a semiconductor material within the doped regions 204 and 206to form metal-containing regions 402, as illustrated in FIG. 4. Themetal-containing layer 302 may include titanium, tantalum, tungsten,cobalt, nickel, platinum, or the like, and the metal-containing regions402 can include a metal silicide compound. Unreacted portions, such asthose overlying the dielectric layer 204 are removed.

In still another embodiment, a resist layer (not illustrated) may beformed over the metal-containing layer 302, and the resist layer can beetched until portions of the metal-containing layer 302 overlying thedielectric layer 202 are exposed. The portions of the metal-containinglayer 302 overlying the dielectric layer 202 are etched, leavingmetal-containing regions 402 within the openings of the dielectric layer202. The remaining resist layer may then be removed. Another technique(e.g., polishing) can be used to form the metal-containing regions 402.In another embodiment (not illustrated), the metal-containing layer 302in FIG. 3 is not patterned and remains over substantially of theworkpiece, including over the dielectric layer 202 and within openingsextending through the dielectric layer 202.

The dielectric layer 202 can be reshaped, as illustrated in FIG. 5. Thereshaping can be performed using a wet or dry etch process. For example,in an embodiment, the reshaping is performed using an HF dip or a plasmaetch. In another embodiment, reshaping can be performed earlier in theprocess as described later in this specification. In a particularembodiment, an angle α as illustrated in FIG. 5 is defined by a side ofthe dielectric layer 202 and the primary side 106. The angle α can be anacute angle, and in an embodiment, the angle α is at least approximately30° or at least approximately 45°, and in another embodiment, the angleα is no greater than approximately 75° or no greater than approximately60°.

Metallic regions 602 are formed as illustrated in FIG. 6. Differenttechniques can be performed to achieve the metallic regions 602. Themetallic regions 602 may be substantially thicker and have a relativelyhigher conductance as compared to the metal-containing regions 402. In aparticular embodiment, the metallic regions 602 are at leastapproximately 11 times, approximately 50 times, or approximately 500times thicker than the metal-containing regions 402.

The metallic regions 602 can include any of the metals or metal alloyspreviously described with respect to the metal-containing regions 402.In a particular embodiment, the metallic regions 602 comprise tin,nickel, chromium, copper, silver, gold, or a combination thereof.Similar to the metal-containing regions 402, the metallic regions 602can include a single film or a plurality of films. In a particularembodiment, the metallic regions 602 can consist essentially of gold,and in another embodiment, the metallic regions 602 can be mostly copperwith a relatively thin indium-tin alloy to help improve soldering duringa subsequent bonding operation. Other combinations of materials can beused such that the composition of the metallic regions 602 is tailoredto a particular application. The metallic regions 602 can be formed byPVD, CVD, ALD, electrochemistry, another suitable method, or anycombination thereof. The metallic regions 602 and the metal-containingregions 402 can include the same composition or different compositionsand be formed using the same technique or different techniques. In anembodiment, metallic regions 602 can have a thickness of at leastapproximately 10 microns or at least approximately 30 microns, and inanother embodiment, the metallic regions 602 can have a thickness nogreater than approximately 2 mm or no greater than approximately 100 mm.

In a particular embodiment, the metallic regions 602 can be formed suchthat a separation-enhancing species is incorporated within the metallicregions 602 when it is formed. As previously described, theseparation-enhancing species can help separate a portion of thesubstrate, in the form of a semiconductor layer, from a remainingportion of the substrate 102. In a particular embodiment, theseparation-enhancing species is hydrogen. When the metallic regions 602is formed using an electrochemical process, such as plating (i.e.,electroplating or electroless plating), hydrogen may be incorporatedfrom the metallic regions 602 from the plating bath, such as an acidicsolution. When a PVD, CVD, or ALD process is used, hydrogen may comefrom a hydrogen-containing gas, such as an organometallic precursor,water vapor, a hydrogen-containing plasma, or any combination thereof.Hydrogen can be moved from the metallic regions 602 in the substrate 102during a subsequent anneal.

In a particular embodiment, the metal-containing regions 402 form atemplate for the growth of the metallic regions 602. An electrochemicaloperation can be performed so that the metallic regions 602 are formedfrom the metal-containing regions 402; however, substantially none oronly an insignificant amount of material is grown from the dielectriclayer 202. In another embodiment, a metal paste including aluminum,nickel, silver, a suitable metal silicate, or any combination thereofcan be pasted on the side of the workpiece closer to the primary sidethan the opposing side of the substrate 102. Polishing can be performedto remove portions of the metallic regions 602 that overlie thedielectric layer 202.

In another embodiment, the separation-enhancing species can be moved byan electrical field. For example, if the hydrogen is positively charged,then a sufficient strong negative charge from the substrate, a positivecharge on the metallic regions 602, or both may be used to move thehydrogen from the metallic regions 602 into the substrate 102. An annealand separation process as previously described can be performed.

Note that the separation-enhancing species can be introduced by anelectrochemical process or by ion implantation as previously described.In a particular embodiment, a combination of ion implantation and anelectrochemical process can be used to provide the separation-enhancingspecies. When both are used, a lower dose for the ion implantation ofthe separation-enhancing species may be used. For example, thecombination may reduce the dose during implant by approximately one totwo orders of magnitude.

During heating or cooling after the anneal, stress can build within thesubstrate 102 and help to separate the combination of the metallicregions 602, the metal-containing regions 402, the dielectric layer 202,the doped regions 204 and 206, and a semiconductor layer 702, which is aportion of the substrate 102, from a remaining portion of the substrate102, as illustrated in FIG. 7. Thus, the location of theseparation-enhancing species 104 in FIG. 6 represents a weak point fromwhich separation may occur due to strain and mismatch of coefficients ofthermal expansion between the materials in the workpiece. The separationmay occur during the heating or cooling or thereafter. For example, amechanical operation may be used to help with the separation. In aparticular embodiment, the separation may occur by cleaving orfracturing the substrate 102 at a location at or near where theseparation is to be performed. A wedge, wire, saw, laser, an acousticaldevice, or any combination thereof may be used to aid in the mechanicalseparation. In another embodiment, a metallic paste can be mechanicallyapplied over the workpiece, and a stiffened or handling substrate can beattached to the metallic paste and used to aid the separation operation.In a particular embodiment, the separation can be analogous to anexfoliation operation. As illustrated in FIG. 7, the semiconductor layer702 remains bonded to the portion of the workpiece which includes themetallic regions 602. The combination of the semiconductor layer 720,the metallic regions 602, and the dielectric layer 202 are thick enoughto be handled mechanically for further processing.

The substrate 102 can be re-used as a handle for another semiconductordevice to be formed. In another embodiment, the substrate 102 ispolished using chemical or mechanical methods or a combination of thesebefore reusing the substrate 102 for a subsequent electronic device.

FIG. 8 illustrates a substantially completed semiconductor device 800.An anti-reflective coating 812, a passivation layer 814, anotherencapsulating layer, or any combination thereof can be formed along theopposite side 806 of the semiconductor layer 702. The layers 812 and 814can be used when the application for the semiconductor device 800 is asa photovoltaic cell. Light or other radiation is received near theopposite side 806 and the contacts (e.g., the metallic regions 602) areformed near the primary side 106. By having the contacts along one side,rather than both sides, more area can be used for receiving radiation.

An electronic device can include the semiconductor device 800 or aplurality of semiconductor devices similar to or different from thesemiconductor device 800. The electronic device can be a solar panelthat includes one or more of the semiconductor devices, wherein thesemiconductor devices are photovoltaic devices. In another embodiment,the electronic device can be a display that includes one or more of thesemiconductor devices, wherein the semiconductor devices are lightemitting devices. In still another embodiment, the electronic device canbe a radiation detector that includes one or more of the semiconductordevices, wherein the semiconductor devices are radiation sensors. Theelectronic device can include different types of semiconductor devices.For example, an electronic device may include a display that includescontrol logic to adjust the intensity of the display based on theambient light level within a room. In this particular electronic device,both light emitting devices and radiation sensors may be used. Afterreading this specification, skilled artisans will appreciate that manydifferent configurations can be used to achieve a wide variety ofapplications.

FIG. 9 illustrates a workpiece in another embodiment, wherein the methodof separation of the semiconductor layers occurs along opposite sides ofthe substrate 102. Any of the previously described processes can be usedfor the method. The embodiment as illustrated in FIG. 9 includes aparticular, non-limiting embodiment. After reading this specification,skilled artisans will appreciate that other embodiments may be usedwithout departing from the concepts described herein.

In the embodiment as illustrated in FIG. 9, the dielectric layers 202and doped regions 204 and 206 are formed along the primary side 106 ofthe substrate 102, and a dielectric layer 922 and doped regions 924 and926 are formed along the opposing side 110 of the substrate 102. Themetal-containing regions 402 and 942 are formed within openings withinthe dielectric layer 202 and 922, respectively, and the metallic regions602 and 962 are formed from the metal-containing regions 402 and 942,respectively. The separation enhancing species can be introduced at oneor more points in the process flow. An anneal cycle allows thesemiconductor layer 702 and 972 to be separated from the substrate 102.

The patterned dielectric layers 202 and 922 can be formed using any ofthe techniques as previously discussed with respect to the dielectriclayer 202 in FIG. 2, and the doped regions 204, 206, 924, 926 can beformed using any of the techniques as previously discussed with respectto the doped regions 204 and 206 in FIG. 2. The metal-containing regions402 and 942 can be formed using any of the techniques as previouslydiscussed with respect to the metal-containing regions 402 in FIG. 4.Reshaping of the dielectric layer 202 and 922 are optional, and ifperformed, can be performed as previously described. The metallicregions 602 and 962 can be formed using any of the techniques aspreviously discussed with respect to the metallic regions 602 in FIG. 6.The separation-enhancing species (not illustrated) and separationtechniques in forming the semiconductor layers 702 and 972 can be formedor performed using any of the techniques as previously discussed withrespect to the separation-enhancing species (at different points in theprocess flow) and the semiconductor 702 in FIG. 7.

With respect to each set of features (i.e., with respect to thedielectric layers 202 and 922, etc.), such features may have the samecomposition or different compositions, the same conductivity type ordifferent conductivity types, may have the same thickness or depth orhave different thicknesses or depths, may include the same number offilms or different numbers of films, may be formed the same formationtechnique or different formation techniques, or may be formed atsubstantially the same time or at different times.

Dual processing embodiments, such as the embodiment previously describedand illustrated in FIG. 9, may allow one or more processing operationsto be performed simultaneously, and thus, increase equipment throughput.The same type of different types of semiconductor devices may be formedalong the opposite sides of the substrate 102.

In still another embodiment, a layer of material may be used to reflectlight or other radiation at locations between the metallic regions 602.Referring to FIG. 10, a dielectric layer 1004 and a reflector 1006 areformed over the dielectric layer 202 and metallic regions 602. Thedielectric layer 1004 can have a relatively high transmission to thetargeted radiation, such as light, ultraviolet radiation, or acombination thereof. The dielectric layer 1004 can include an oxide, anitride, or any combination thereof. The dielectric layer 1004 can beused to electrically insulate the metallic regions 602 from thereflector 1006 when the reflector 1006 includes a conductive material.In an embodiment, the dielectric layer 1004 can have a thickness of atleast approximately 1 nm or at least approximately 100 nm, and inanother embodiment, the dielectric layer 1004 can have a thickness nogreater than approximately 1000 microns or no greater than approximately1 microns.

The reflector 1006 can include a reflective material and can includesilicon, silver, aluminum, nickel, another suitable material that canprovide a mirror-like finish, or any combination thereof. The reflector1006 can be formed using any of the techniques previously described withrespect to the metal-containing layer 302 or the metallic regions 602.Because the reflector 1006 is principally used for reflection, itsthickness can vary from very thin to very thick. In an embodiment, thereflector 1006 can have a thickness of at least approximately 2 nm or atleast approximately 30 nm, and in another embodiment, the reflector 1006can have a thickness no greater than approximately 2 mm or no greaterthan approximately 100 mm.

In another embodiment, the reflector 1006 can include an insulator, suchas TiO₂, Ta₂O₅, another suitable material, or any combination thereof.In this particular embodiment, the dielectric layer 1004 may not beneeded and can be omitted.

The reflector 1006, and optional dielectric layer 1004, may be formedany time after the metallic regions 602 are formed. Thus, in aparticular embodiment, the reflector 1006 may be formed before theseparation is performed. In this embodiment, the reflector 1006 may havea thickness, such that it provides sufficient mechanical support to thesubsequently formed semiconductor layer 702. A separation-enhancingspecies can be introduced into the substrate 102 during formation of thereflector 1006 instead or in addition to earlier processing. When thereflector 1006 is used and sufficiently thick, the thickness of themetallic regions 602 may not need to be as thick.

In another embodiment, a dielectric layer can be patterned to formangled dielectric regions, such as those illustrated in FIGS. 11 and 12.The angled regions act as Lambertian reflectors a metallic layeroverlies the angled dielectric regions. The patterning may be performedusing a wet etch, a dry etch, or a combination thereof. Also, thedielectric layer can include a plurality of films, a film with a varyingcomposition (e.g., increasing or decreasing amount of phosphorus orother dopant within the film), or any combination thereof. Thepatterning may also occur by a reverse patterning technique as describedwith respect to FIG. 12.

FIG. 11 illustrates a semiconductor device in another embodiment whereinthe dielectric layer 202 is replaced by a patterned dielectric layer1102 having triangular shapes. Another dielectric layer 1104 andreflector 1106 are similar to the dielectric layer 1004 and reflector1006 as described with respect to FIG. 10. In this particularembodiment, the dielectric layers 1102 and 1104 can be substantiallytransparent to the radiation designed to be received by or emitted fromthe semiconductor device. The reflector 1106 can have a minor-likefinish. Thus, the combination of the patterned dielectric layer 1102 andreflector 1106 to form a Lambertian reflector. In another embodiment(not illustrated), the dielectric layer may be replaced with aconductive oxide to get the proper refractive properties of the oxideand the conductive properties of an interconnect. In this particularembodiment, only a single doped region or no doped region may lie alongthe primary side 106 of the semiconductor layer 702.

FIG. 12 illustrates a semiconductor device that has a different aLambertian reflector. As compared to FIG. 11, the patterned dielectriclayer 1202 has features with wider widths as distance from thesemiconductor layer 702 increases. A reverse patterning technique may beused to achieve the shapes as illustrated in FIG. 12. A patternedsacrificial layer (not illustrated) formed at locations between thefeatures of the subsequently-formed patterned dielectric layer 1202 willlie. After forming the patterned dielectric layer 1202, the patternedsacrificial layer is removed. The patterned sacrificial layer can formedwith a single feature or a combination of features (e.g.,cross-sectional rectangular shapes with sidewall spacers). Othertechniques can be used to form the patterned dielectric layer 1202.

Another dielectric layer 1204 and reflector 1206 are similar to thedielectric layer 1004 and reflector 1006 as described with respect toFIG. 10. In this particular embodiment, the dielectric layers 1202 and1204 can be substantially transparent to the radiation designed to bereceived by or emitted from the semiconductor device. The reflector 1206can have a minor-like finish. Thus, the combination of the patterneddielectric layer 1202 and reflector 1206 to form a Lambertian reflector.In another embodiment (not illustrated), a single doped region or nodoped region may be formed along the primary side 106 of thesemiconductor layer 702. In this particular embodiment, ametal-containing layer, such as a seed layer may be patterned to havefeatures with shapes similar to the features of the patterned dielectriclayer 1202.

In another embodiment, the reshaping operation as described with respectto FIG. 5 may be performed earlier in the process. Referring to FIG. 2,the dielectric layer 202 can be formed from a single insulating film ora plurality of insulating films that are deposited over the workpiece.In a particular embodiment, the characteristics of the dielectric layer202 may be different for points closer to the substrate 102 as comparedto corresponding points further from the substrate 102. In anembodiment, the composition of the dielectric layer 202 may changeduring or between depositions when the dielectric layer includes aplurality of films. For example, an oxide film may be closer to thesubstrate 102, and a nitride film may be deposited over the oxide film.In another embodiment, a dopant, such as phosphorus, can be incorporatedat an increasing concentration during a later part of the deposition.

In a further embodiment, the dielectric layer 202 may include boron,phosphorous, another suitable dopant or any combination thereof. When ananneal is performed to activate dopants within the doped regions 204 and206, the dielectric layer 202 may be reflowed to round the upper cornersof the dielectric layer 202. In still another embodiment, the stresswithin the dielectric layer 202 can be changed by changing depositionparameters (e.g., radio frequency power, pressure, etc.) even though thecomposition is substantially the same throughout the thickness of thedielectric layer 202. In further embodiments, combinations of theforegoing may be used. When etching is performed to form the openingsthrough the dielectric layer 202, etching can be performed such thatisotropic etching is used for etching a portion of the dielectric layer202, alternative etching the insulating material and etching a sidewalletch of the overlying mask, etching the insulating material and etchinga sidewall etch of the overlying mask, taking advantage of adifferential composition (doped oxide etches faster than undoped oxide),patterning followed by a sidewall spacer, another suitable technique, orany combination thereof. Many of the techniques described in shaping thedielectric layer 202 may be used in forming the patterned layers for theLambertian reflectors in FIGS. 11 and 12.

Embodiments previously described may use substrates that are in a waferform. In another embodiment, the substrate may be in an ingot form. In aparticular embodiment as illustrated in FIG. 13, the substrate 1302 canbe substantially cylindrical. Such a substrate can be made from a boulegrown using a Czochralski growth technique and machined to the desiredshape. The ingot can have a diameter of approximately 50 mm toapproximately 300 mm or even larger. The length of the ingot can begreater than the diameter and can range from approximately 150 mm toapproximately 5 meters. The substrate 1302 can include any of thematerials are previously described with respect to the substrate 102.The workpiece 1300 further includes a doped region 1304, ametal-containing region 1306, and a metallic region 1308, which canincludes any of the materials, have any of the thicknesses, and beformed using any of the techniques as previously described with respectto the doped regions 204, the metal-containing regions 402, and themetallic regions 602, respectively, as previously described. Aseparation-enhancing species (not illustrated) can be introduced intothe workpiece during an ion implantation operation, during formation ofthe metallic regions 602, or both. After reading this specification,skilled artisans will appreciate that one or more of the regions orfilms of the workpiece 1300 are not required and may not be used, andthat other regions or films as previously described but are notillustrated may be used.

The conductive film 1308 can be scored, perforated, or cut to provide aweakened location from which separation can more readily start. Theworkpiece 1300 is then annealed using annealing conditions as previouslydescribed. During heating or cooling after the anneal, stress can buildwithin the substrate 1302 and help to separate the combination of theconductive film 1308, the metal-containing film 1306, the doped region1304, and a semiconductor layer 1410, which is a separated portion ofthe substrate 1302, from a remaining portion of the substrate 1302, asillustrated in FIG. 14. The embodiment of FIG. 14 also illustrates apatterned dielectric layer 1402 and doped regions 1406, which canincludes any of the materials, have any of the thicknesses, and beformed using any of the techniques as previously described with respectto the dielectric layer 202, the doped regions 206, respectively, aspreviously described. The resultant workpiece 1400 can be furtherprocessed to form a semiconductor device. In this particular embodiment,the semiconductor device can be in the form of a rectangular sheet, asopposed to a circular disk. In still another embodiment, the substratesmay be substantially rectangular and be formed using an edge-definedgrowth technique.

The embodiments described herein can be used to forming contacts on oneside of a substrate while using separation technique to be performed. Ina particular embodiment, a separation-enhancing species to be introducedinto a substrate to allow more readily the separation of a surface layerof semiconductor material to be removed from the substrate. A mechanicaloperation may not need to be performed for the separation, or if amechanical operation is used, such mechanical operation would not needto be as aggressive or damaging as compared to a mechanical tearingoperation performed in the absence of the separation-enhancing species.Further, the doped regions and contacts can be formed along a sideopposite where light or other radiation would be received by anelectronic device. Thus, the efficiency is improved as contacts,interconnects, and the like are not formed along the radiation receivingsurface of the electronic device.

Many different aspects and embodiments are possible. Some of thoseaspects and embodiments are described below. After reading thisspecification, skilled artisans will appreciate that those aspects andembodiments are only illustrative and do not limit the scope of thepresent invention.

In a first aspect, a method can include forming a first junction in thesemiconductor substrate, and forming a region of hydrogen in thesemiconductor substrate. The method can also include forming adielectric layer over a first side of a semiconductor substrate, andpatterning the dielectric layer to form a patterned dielectric layerdefines an opening. The method can further include forming a firstmetallic layer over the patterned dielectric layer and within theopening, and annealing the first metallic layer to form a silicidelayer. The method can still further include forming a second metalliclayer over the silicide layer, wherein the second metallic layer isformed using an electrochemical process, and separating a combination ofthe first metallic layer, the second metallic layer, and a semiconductorlayer by a process of anneal and strain induced by the second metalliclayer.

In an embodiment of the first aspect, the method further includes movingthe hydrogen from the second metallic layer into the semiconductorsubstrate, wherein moving the hydrogen from the second metallic layerinto the semiconductor substrate is used to weaken regions of thesemiconductor substrate to aid in separating the semiconductor layerfrom the semiconductor substrate. In another embodiment, the region ofhydrogen in the semiconductor is formed by implantation. In stillanother embodiment, forming a region of hydrogen in the semiconductorsubstrate includes forming a first region of hydrogen to a first depthin the semiconductor substrate, and forming a second region of hydrogento a second depth in the semiconductor substrate, wherein the firstdepth is different from the second depth. In a particular embodiment,each of the acute angles is no greater than approximately 75°. Inanother particular embodiment, the method further includes forming athird metallic layer on the dielectric regions to act as reflectors oflight. In a further particular embodiment, the method further includesforming an insulating layer over the second metallic layer; and forminga third metallic layer over the insulating layer, wherein the thirdmetallic layer reflects light at locations between conductive memberswithin the second metallic layer.

In a further embodiment of the first aspect, the first metallic layer isformed by physical vapor deposition, atomic layer deposition, chemicalvapor deposition, or any combination thereof. In still a furtherembodiment, the second metallic layer includes titanium, tungsten,palladium, copper, tin, nickel, or any combination thereof. In still afurther embodiment, the forming the metallic layer further includesmechanically applying a metallic paste over the semiconductor substrate.In yet a further embodiment, the semiconductor substrate includessilicon, germanium, gallium arsenide, gallium nitride, indium phosphide,or any combination thereof.

In another embodiment of the first aspect, the semiconductor device is aphotovoltaic cell or a light emitting device. In still anotherembodiment, the method further includes forming a second junction spacedapart from the first junction. In a particular embodiment, the silicidelayer is formed at least partly from a semiconductor material within thefirst and second junctions. In a more particular embodiment, the firstjunction has a different polarity as compared to the second junction.

In a second aspect, a method of forming an electronic device can includeforming a first patterned layer adjacent to a first side of a substrateincluding a semiconductor material. The method can also includeseparating a first semiconductor layer and the first patterned layerfrom the substrate, wherein the first semiconductor layer is a firstportion of the substrate.

In an embodiment of the second aspect, the substrate is a substantiallymonocrystalline semiconductor substrate. In another embodiment, thesubstrate principally includes silicon, germanium, gallium arsenide,gallium nitride, indium phosphide, or any combination thereof. In stillanother embodiment, the method further includes introducing a firstseparation-enhancing species into the substrate at a first distance fromthe first side. In a particular embodiment, introducingseparation-enhancing species includes implanting a separation-enhancingspecies at an energy corresponding to a projected range that is closerthe first distance than to the first side. In a more particularembodiment, the projected range is substantially equal to the firstdistance. In another more particular embodiment, theseparation-enhancing species includes hydrogen, helium, or boron.

In a further embodiment of the second aspect, the method furtherincludes annealing the substrate and the first patterned layer. In stilla further embodiment, the method further includes doping a first regionadjacent to the first side of the substrate. In yet a furtherembodiment, forming the first patterned layer includes forming apatterned dielectric layer. In a particular embodiment, the methodfurther includes doping a first region of the substrate adjacent to anopening within the patterned dielectric layer. In a more particularembodiment, the method further includes doping a second region of thesubstrate with a dopant having a conductivity type opposite that of thefirst portion, wherein the first and second regions lie along the firstside of the substrate and are spaced apart from each other.

In another particular embodiment of the second aspect, the methodfurther includes forming a first metallic layer within openings withinthe patterned dielectric layer. In a more particular embodiment, themethod further includes reacting a portion of the first metallic layerwith a semiconductor material within the substrate to form ametal-silicide compound and removing an unreacted portion of the firstmetallic layer. In still another particular embodiment, forming thepatterned dielectric layer includes forming a dielectric region having asidewall and a bottom, wherein the sidewall and bottom define an acuteangle. In a more particular embodiment, the acute angle is no greaterthan approximately 75°. In another particular embodiment, the methodfurther includes forming a metallic member partly formed on the sidewallof the dielectric region.

In another embodiment of the second aspect, forming the first patternedlayer includes forming a patterned metal layer. In a particularembodiment, forming the patterned metal layer includes forming a firstmetallic member adjacent to the first side and electrically connected toa first doped region within the substrate. In a more particularembodiment, forming the patterned metal layer includes forming a secondmetallic member adjacent to the first side and electrically connected toa second doped region within the substrate, wherein the first and seconddoped regions have opposite conductive types and are spaced apart fromeach other.

In another particular embodiment of the second aspect, the methodfurther includes introducing a first separation-enhancing species intothe substrate at a first distance from the first side during or afterforming the patterned metal layer. In a more particular embodiment, thefirst patterned metal layer includes titanium, tungsten, palladium,copper, tin, nickel, or any combination thereof. In another moreparticular embodiment, the method further includes forming ametal-silicide member, wherein the forming the first patterned metallayer is performed after forming the metal-silicide member. In stillanother more particular embodiment, forming the first patterned metallayer further includes forming an adhesion film, a barrier film, a seedfilm, or any combination thereof.

In yet another more particular embodiment of the second aspect, formingthe first patterned metal layer is performed using physical vapordeposition, atomic layer deposition, chemical vapor deposition, anelectrochemical process, or any combination thereof. In an even moreparticular embodiment, forming the first patterned metal layer isperformed using a hydrogen-containing gas. In a further more particularembodiment, incorporating the first separation-enhancing speciesincludes incorporating hydrogen into the first patterned metal layer;and moving the hydrogen from the first patterned metal layer into thesubstrate. In an even more particular embodiment, forming the firstpatterned metal layer is performed using an acidic solution as a sourceof hydrogen. In another more particular embodiment, forming the firstpatterned metal layer and incorporating hydrogen into the firstpatterned metal layer occur substantially simultaneously during aparticular time period.

In a further embodiment of the second aspect, separating the firstsemiconductor layer and the first patterned layer from the substrateincludes mechanically separating the first semiconductor layer and thefirst patterned layer from the substrate. In a particular embodiment,mechanically separating the first semiconductor layer and the firstmetallic layer from the substrate is performed using a wedge, a wire, ora saw, laser, or an acoustical device. In still a further embodiment,separating the first semiconductor layer and the first patterned layerfrom the substrate includes fracturing or cleaving the substrate atsubstantially the first distance from the first side of the substrate.In yet a further embodiment, after separating the first semiconductorlayer and the first patterned layer from the substrate, the firstpatterned layer is thicker than the first semiconductor layer. Inanother embodiment, the method further includes attaching a supportmember to a combination of the substrate and the first patterned layer,wherein the support member is closer to the first side of the substrateas compared to an opposite side of the substrate. The method alsoincludes removing the support member after separating the firstsemiconductor layer and the first patterned layer from the substrate.

In still another embodiment of the second aspect, the method furtherincludes forming an antireflective layer adjacent to a second side ofthe first semiconductor layer, wherein the second side is opposite thefirst side. In a particular embodiment, the antireflective layer isdesigned to have a reduced reflectance for a first wavelength less than500 nm, and in another embodiment, the antireflective layer is designedto have an increased reflectance for a second wavelength greater than700 nm. In a particular embodiment, the first wavelength isapproximately a first multiple of a first particular wavelength in arange of 290 nm to 400 nm, and the second wavelength is approximatelythe first particular wavelength times a sum of a whole number plus 0.5.

In a further embodiment, the method further includes forming a reflectoradjacent to a second side of the first semiconductor layer, wherein thesecond side is opposite the first side. In a particular embodiment, thereflector includes a Lambertian reflector. In yet a further embodiment,the electronic device includes a photovoltaic cell that includes thefirst semiconductor layer and the first metallic layer, a light emittingdevice that includes the first semiconductor layer and the firstmetallic layer, a radiation detector that includes the firstsemiconductor layer and the first metallic layer, or any combinationthereof.

In another embodiment of the second aspect, the method further includesforming a second patterned layer adjacent to a second side of thesubstrate and separating a second semiconductor layer and the secondpatterned layer from the substrate, wherein the second semiconductorlayer is a second portion of the substrate. In a particular embodiment,forming the first patterned layer and forming a second patterned layerare performed substantially simultaneously during a first time period.In another particular embodiment, a combination of the firstsemiconductor layer and first patterned layer is of a firstsemiconductor device type, a combination of the second semiconductorlayer and second patterned layer is of the first semiconductor devicetype, and a thickness of the first semiconductor layer is substantiallythe same as a thickness of the second semiconductor layer. In stillanother particular embodiment, a combination of the first semiconductorlayer and first patterned layer is of a first semiconductor device type,a combination of the second semiconductor layer and second patternedlayer is of a second semiconductor device type, a thickness of the firstsemiconductor layer is different from a thickness of the secondsemiconductor layer.

Note that not all of the activities described above in the generaldescription or the examples are required, that a portion of a specificactivity may not be required, and that one or more further activitiesmay be performed in addition to those described. Still further, theorder in which activities are listed is not necessarily the order inwhich they are performed.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any feature(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature of any or all the claims.

The specification and illustrations of the embodiments described hereinare intended to provide a general understanding of the structure of thevarious embodiments. The specification and illustrations are notintended to serve as an exhaustive and comprehensive description of allof the elements and features of apparatus and systems that use thestructures or methods described herein. Separate embodiments may also beprovided in combination in a single embodiment, and conversely, variousfeatures that are, for brevity, described in the context of a singleembodiment, may also be provided separately or in any subcombination.Further, reference to values stated in ranges includes each and everyvalue within that range. Many other embodiments may be apparent toskilled artisans only after reading this specification. Otherembodiments may be used and derived from the disclosure, such that astructural substitution, logical substitution, or another change may bemade without departing from the scope of the disclosure. Accordingly,the disclosure is to be regarded as illustrative rather thanrestrictive.

What is claimed is:
 1. A method of forming an electronic devicecomprising: forming a first patterned layer adjacent to a first side ofa substrate including a semiconductor material; and separating a firstsemiconductor layer and the first patterned layer from the substrate,wherein the first semiconductor layer is a first portion of thesubstrate.
 2. The method of claim 1, further comprising introducing afirst separation-enhancing species into the substrate at a firstdistance from the first side.
 3. The method of claim 2, wherein theseparation-enhancing species includes hydrogen, helium, or boron.
 4. Themethod of claim 1, further comprising annealing the substrate and thefirst patterned layer.
 5. The method of claim 1, further comprisingdoping a first region adjacent to the first side of the substrate. 6.The method of claim 1, wherein forming the first patterned layercomprises forming a patterned dielectric layer.
 7. The method of claim6, wherein forming the patterned dielectric layer includes forming adielectric region having a sidewall and a bottom, wherein the sidewalland bottom define an acute angle that is no greater than approximately75°.
 8. The method of claim 7, further comprising forming a metallicmember partly formed on the sidewall of the dielectric region.
 9. Themethod of claim 1, wherein forming the first patterned layer comprisesforming a patterned metal layer.
 10. The method of claim 9, whereinforming the patterned metal layer comprises forming a first metallicmember adjacent to the first side and electrically connected to a firstdoped region within the substrate.
 11. The method of claim 9, furtherincluding introducing a first separation-enhancing species into thesubstrate at a first distance from the first side during or afterforming the patterned metal layer.
 12. The method of claim 11, whereinincorporating the first separation-enhancing species comprises:incorporating hydrogen into the first patterned metal layer; and movingthe hydrogen from the first patterned metal layer into the substrate.13. The method of claim 12, wherein forming the first patterned metallayer is performed using an acidic solution as a source of hydrogen. 14.The method of claim 12, wherein forming the first patterned metal layerand incorporating hydrogen into the first patterned metal layer occursubstantially simultaneously during a particular time period.
 15. Themethod of claim 1, wherein separating the first semiconductor layer andthe first patterned layer from the substrate comprises mechanicallyseparating the first semiconductor layer and the first patterned layerfrom the substrate.
 16. The method of claim 15, wherein mechanicallyseparating the first semiconductor layer and the first metallic layerfrom the substrate is performed using a wedge, a wire, or a saw, laser,or an acoustical device.
 17. The method of claim 1, wherein separatingthe first semiconductor layer and the first patterned layer from thesubstrate comprises fracturing or cleaving the substrate atsubstantially the first distance from the first side of the substrate.18. The method of claim 1, wherein the electronic device comprises aphotovoltaic cell that includes the first semiconductor layer and thefirst metallic layer.
 19. A method of forming an electronic devicecomprising: forming a doped region adjacent to a side of a substrate;forming a first patterned layer adjacent to a first side of a substrateincluding a semiconductor material; plating a metal-containing layerover the patterned dielectric layer; cooling or heating themetal-containing layer after plating the metal-containing layer, whereina weak point is formed within the substrate as a result of cooling orheating the metal-containing layer; and mechanically separating a firstsemiconductor layer, the first patterned layer, and the metal-containinglayer from the substrate, wherein mechanically separating occursadjacent to the weak point within the substrate, and the firstsemiconductor layer is a first portion of the substrate.
 20. The methodof claim 19, wherein mechanically separating is performed using a wedge.